1. Field of the Invention
The present invention relates to a static memory (SRAM) cell and, more particularly, to a static memory cell used in a BiCMOS technique in which a bipolar transistor and a CMOS circuit are formed on the same substrate.
2. Description of the Related Art
FIG. 1 is a circuit diagram showing a conventional static memory cell having four high-resistance load transistors often used in a CMOS SRAM. Resistor elements R1 and R2 and n-channel MOSFETs (NMOSFET) Q1 and Q2 cross-connected to each other are connected between a positive potential power source 1 and a negative potential power source (ground potential) to obtain a flip-flop. The flip-flop is used as a memory cell. A word line WL is connected to the gates of access transistors Q3 and Q4. The access transistors Q3 and Q4 are selected by the word line WL and have drains respectively connected to internal nodes A and B for extracting complementary outputs of the flip-flop and sources respectively connected to a pair of complementary bit lines BL and BL.
In both read and write operations, the word line WL connected to a memory cell to be selected is set to be a high potential. In the read operation, when the pair of bit lines BL and BL are charged to a high potential such that cell data is not inverted, and a cell current flows in a low-potential side bit line of the pair of bit lines BL and BL of the nodes A and B to pull down bit line to the low-potential side, a potential difference occurs between the bit lines BL and BL. This potential difference is read out by a differential sense amplifier. In the write operation, after the word line WL is selected, a high-potential signal is input to one of the bit lines BL and BL, and a low-potential signal is input the other of the bit lines BL and BL, thereby updating data of the flip-flop of the memory cell.
In this high-resistance load memory cell, the word line of a non-selected cell, i.e., a waiting cell, must be set to be the same potential as the low-potential power source due to the following reason. The access transistors Q3 and Q4 connected to the word line WL of the waiting cell are turned on at an intermediate potential except for the potential of the low potential power source, and a cell current flows from the bit line through the access transistors, thereby increasing power consumption during the waiting operation. Therefore, a CMOS logic circuit must be used for selecting a word line.
This condition is not changed even when a BiCMOS technique which has been used in a high speed, large-capacity SRAM is employed as in recent years, as long as a memory cell having the above arrangement is used. In a BiCMOS SRAM, especially an ECL BiCMOS SRAM having an input/output mode applied for an ECL, in order to shorten an access time almost equal to that of an ECL bipolar SRAM, all peripheral circuits are preferably constituted by ECL logic circuits which are operated at a speed higher than a CMOS logic circuit.
However, in order to prevent an increase in power consumption of a non-selected memory cell, a CMOS logic circuit must be used as a circuit for driving a word line. This is because an output having the same potential as that of the low-potential power source cannot be theoretically obtained by the ECL logic circuit. For this reason, when the CMOS circuit is used as a word line drive circuit, the operation speed is decreased compared with a case wherein the ECL circuit is used as the word line drive circuit. In addition, since an ECL logic level must be converted into a CMOS logic level, an access time is disadvantageously further prolonged by the conversion time.
As a means for solving the above problem, a memory cell shown in circuit diagram of FIG. 2 is proposed. In this memory cell, a flip-flop is constituted by NMOSFETs Q1 and Q2 cross-connected to each other and p-channel MOSFETs Q5 and Q6. The sources of the NMOSFETs are connected to a negative potential power source (ground potential), and the sources of the PMOSFETs are connected to a read word line RWL. In addition, an internal node A is connected to a write bit line WBL through an access transistor Q3 selected by a write word line WWL and having the gate connected to the write word line WWL. An internal node B is connected to a read bit line RBL through an npn bipolar transistor T1 having the base connected to the internal node B, the collector connected to a positive potential power source, and the emitter connected to the read bit line RBL. A sense amplifier 11 constituted by an npn transistor T.sub.REF, a resistor R.sub.REF, and a constant current source 12 is connected to the read bit line RBL.
A write operation of the memory cell in FIG. 2 is performed as shown in FIG. 1. That is, the write word line WWL is set to be a high potential during the write operation to turn on the access transistor Q3, the internal node A is connected to the write bit line WBL, and a high or low potential is applied to the write bit line WBL from an external circuit, thereby updating data of the flip-flop. During a period except for the write operation, the write word line WWL is set to be the same potential as that of the low-potential power source.
A read operation of the memory cell is largely different from that of the memory cell shown in FIG. 1. The read word line RWL is set to be a higher potential during the reading operation than that during the waiting operation. The read bit line RBL is charged to a potential V.sub.REF -Vf (Vf is a forward biasing base-emitter potential of the npn transistor T.sub.REF, e.g., about 0.8 V) through the sense amplifier 11. A selection potential V.sub.RWLH of the read word line RWL during a selecting operation is set to be higher than the potential V.sub.REF. In this case, when the node B is set to be a high potential during a cell selecting operation, a differential amplifier is constituted by the npn bipolar transistor T1 and the sense amplifier T.sub.REF, and the potential of the read bit line RBL is set to be "V.sub.RWLH -Vf&gt;V.sub.REF -Vf" to cut off the transistor T.sub.REF. Subsequently, an output OUT is charged by the load resistor R.sub.REF to output a high-potential output. On the other hand, when the node B is set to be a low potential, i.e., the potential of the low-potential power source, the potential of the read bit line RBL is held at a potential "V.sub.REF -Vf", the transistor T.sub.REF is turned on, and the transistor T1 is cut off. The output OUT outputs a low-potential output. As described above, the potential of the high-potential power source of the memory cell is applied to the read word line RWL to amplify the read word line RWL at a intermediate potential, and the read word line RWL can be driven by the ECL logic circuit. Therefore, even in the ECL BiCMOS SRAM, the same access time as that of the ECL bipolar SRAM can be obtained.
Although the memory cell in FIG. 1 is constituted by four NMOSFETs, the memory cell in FIG. 2 is constituted by three NMOSFETs, two PMOSFETs, and one npn bipolar transistor. Therefore, although the cell size of the memory cell in FIG. 2 is smaller than that of a bipolar memory cell, it becomes three or four times the memory cell in FIG. 1 to disable an increase in integration density. More specifically, when a PMOSFET and an NMOSFET are to be integrated in a single memory cell, an n-type well region for forming the PMOSFET must be isolated from a p-type well region for forming the NMOSFET in the memory cell by an isolation region. This is the most serious obstacle against a decrease in cell size.